Solid-state image sensors have found widespread use in camera systems. The solid-state imager sensors in some camera systems are composed of a matrix of photosensitive elements in series with switching and amplifying elements. The photosensitive sensitive elements may be, for example, photoreceptors, photo-diodes, phototransistors, charge-coupled device (CCD), gates, or the like. Each photosensitive element receives an image of a portion of a scene being imaged. A photosensitive element along with its accompanying electronics is called a picture element or pixel. The image obtaining photosensitive elements produce an electrical signal indicative of the light intensity of the image. The electrical signal of a photosensitive element is typically a current, which is proportional to the amount of electromagnetic radiation (light) falling onto that photosensitive element.
Of the image sensors implemented in a complementary metal-oxide-semiconductor (CMOS)- or MOS-technology, image sensors with passive pixels and image sensors with active pixels are distinguished. The difference between these two types of pixel structures is that an active pixel amplifies the charge that is collected on its photosensitive element. A passive pixel does not perform signal amplification and requires a charge sensitive amplifier that is not integrated in the pixel.
FIG. 1A illustrates one embodiment of a conventional pixel structure used within a synchronous shutter image sensor. A synchronous shutter image sensor is used to detect the signal of all the pixels within the array at approximately the same time. This is in contrast to an asynchronous shutter image sensor that may be implemented with a 3T (three transistor) or 4T (four transistor) pixel structure that does not include a sample and hold stage. Such an asynchronous shutter image sensor outputs the state of a pixel at the moment of read out. This gives movement artifacts because every pixel in the array is not sensing a scene at the same moment.
The pixel structure of FIG. 1A that is used in a synchronous shutter image sensor includes a light detecting stage and a sample and hold stage. The light detecting stage includes a photodiode, a reset transistor and a unity gain amplifier). The sample and hold stage includes a sample transistor, one or more memory capacitors (represented by the capacitor C in FIG. 1A), a sample buffer and a multiplexer, i.e., switch or select transistor coupled to a column output of the pixel array.
FIG. 1B illustrates one conventional 6 transistor (“6T”) pixel circuit configuration of the synchronous pixel of FIG. 1A. The reset transistor of the light detecting stage is used to reset the pixel to a high value, and then the voltage on the gate of the source follower transistor M1 starts dropping due to the photocurrent generated in the photodiode. The source follower transistor M1 operates as a unity gain amplifier to buffer the signal from the photodiode. The sample and hold (S&H) stage of FIG. 1B “sample” loads the voltage signal of source follower transistor M1, through the sample transistor, on the memory capacitor (Cmem). The voltage signal from the source follower transistor M1 will remain on the memory capacitor when the sample transistor is turned off. The memory capacitor should be pre-charged to a starting staring voltage before sampling occurs. The pre-charge transistor serves to pre-charge the voltage on Cmem to a low voltage level upon application of the pre-charge pulse to the gate of the pre-charge transistor, with the source of the pre-charge transistor being tied to ground (GND).
FIG. 2 illustrates a portion of a conventional layout structure for the 6T pixel of FIG. 1B. It should be noted that the layout of FIG. 2 does not include all the layers (e.g., the metal layer that connects the two storage node vias to Cmem). In the conventional layout illustrated in FIG. 2, the sample transistor has a gate that stretches linearly across the active region such that it only borders the portion of the active region (forming the sample transistor source, pre-charge transistor drain, and storage node) of one side (labeled “side A”) of the active region and does not border the other sides of the active region (labeled “side B”, “side C” and “side D”).
In the pixel layout illustrated in FIG. 2, the parasitic junction in between the sample transistor gate and the pre-charge transistor gate of the storage node is not fully shielded from laterally diffusing charges such that it collects charges from the substrate resulting in a parasitic light sensitivity (PLS). Some conventional pixels structures reduce parasitic light sensitivity (PLS) by reducing to a minimum the parasitic junction area and covering it with a metal light shield. As the junction area is minimized, it collects less charge from the pixel substrate. When covered with a metal light shield, fewer charges are generated inside or close to the parasitic junction.
Although the PLS obtained with conventional structures discussed above is good in some image sensor application, it may not be suitable for certain applications. In particular, the PLS of conventional pixel structures in synchronous shutter image sensors may be too high.